Index: u-boot/cpu/arm920t/start.S
===================================================================
--- u-boot.orig/cpu/arm920t/start.S
+++ u-boot/cpu/arm920t/start.S
@@ -35,6 +35,8 @@
 #include <s3c2410.h>
 #elif defined(CONFIG_S3C2440) || defined(CONFIG_S3C2442)
 #include <s3c2440.h>
+#elif defined(CONFIG_S3C2443)
+#include <s3c2443.h>
 #endif
 #include <status_led.h>
 
@@ -171,7 +173,7 @@ copyex:
 #endif
 
 #if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) || \
-    defined(CONFIG_S3C2442)
+    defined(CONFIG_S3C2442) || defined(CONFIG_S3C2443)
 	/* turn off the watchdog */
 
 # if defined(CONFIG_S3C2400)
@@ -212,6 +214,11 @@ copyex:
 # endif
 # define CLKDIVN_val  7 /* FCLK:HCLK:PCLK = 1:3:6 */
 # define CAMDIVN      0x4C000018
+#elif defined(CONFIG_S3C2443)
+# define INTSUBMSK_val        0x1fffffff
+# define EPLLCON_val  ((40 << 16) | (1 << 8) | (1))           /* 96 MHz */
+# define MPLLCON_val  ((81 << 16) | (2 << 8) | (0))           /* 1068 MHz */
+# define CLKDIV0_val  ((8 << 9) | (1 << 4) | (1 << 3) | (1 << 2)
 #endif
 
 	ldr     r0, =pWTCON
@@ -224,7 +231,8 @@ copyex:
 	mov	r1, #0xffffffff
 	ldr	r0, =INTMSK
 	str	r1, [r0]
-# if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) || defined(CONFIG_S3C2442)
+# if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) || defined(CONFIG_S3C2442) || \
+     defined(CONFIG_S3C2443)
 	ldr	r1, =INTSUBMSK_val
 	ldr	r0, =INTSUBMSK
 	str	r1, [r0]
@@ -243,6 +251,43 @@ copyex:
 	mcr	p15, 0, r1, c1, c0, 0
 
 
+#if defined(CONFIG_S3C2443)
+#define LOCKCON0	0x4c000000
+#define LOCKCON1	0x4c000004
+#define MPLLCON		0x4c000010
+#define EPLLCON		0x4c000018
+
+	ldr	r0, =CLKDIV0
+	ldr	r1, =CLKDIV0_val
+	str	r1, [r0]
+
+	/* set safe (way too long) locktime for both PLLs */
+	ldr	r0, =LOCKCON0
+	mov	r1, #0xffffff
+	str	r1, [r0]
+	ldr	r0, =LOCKCON1
+	str	r1, [r0]
+
+	/* configure MPLL */
+	ldr	r0, =MPLLCON
+	ldr	r1, =MPLLCON_val
+	str	r1, [r0]
+
+	/* select MPLL clock out for SYSCLK */
+	ldr	r0, =CLKSRC
+	ldr	r1, [r0]
+	orr	r1, r1, #0x10
+	str	r1, [r0]
+
+#if 0
+	/* configure EPLL */
+	ldr	r0, =EPLLCON
+	ldr	r1, =EPLLCON_val
+	str	r1, [r0]
+#endif
+
+
+#else /* i.e. 2440, 2410 and 2440 */
 #define LOCKTIME	0x4c000000
 #define UPLLCON		0x4c000008
 
@@ -270,6 +315,7 @@ copyex:
 	ldr	r0, =CLKDIVN
 	mov	r1, #CLKDIVN_val
 	str	r1, [r0]
+#endif
 
 #if 1
 	/* enable uart */
@@ -296,7 +342,8 @@ copyex:
 	str	r1, [r0, #0x28]
 #endif
 
-#endif	/* CONFIG_S3C2400 || CONFIG_S3C2410 || CONFIG_S3C2440 || CONFIG_S3C2442 */
+#endif	/* CONFIG_S3C2400 || CONFIG_S3C2410 || CONFIG_S3C2440 || CONFIG_S3C2442
+	   CONFIG_S3C2443 */
 
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 #ifndef CONFIG_LL_INIT_NAND_ONLY
@@ -304,7 +351,8 @@ copyex:
 #endif
 
 #if defined(CONFIG_AT91RM9200) || defined(CONFIG_S3C2410) || \
-    defined(CONFIG_S3C2440) || defined(CONFIG_S3C2442)
+    defined(CONFIG_S3C2440) || defined(CONFIG_S3C2442) || \
+    defined(CONFIG_S3C2443)
 
 #ifndef CONFIG_SKIP_RELOCATE_UBOOT
 	adr	r0, _start		/* r0 <- current position of code   */
Index: u-boot/cpu/arm920t/s3c24x0/interrupts.c
===================================================================
--- u-boot.orig/cpu/arm920t/s3c24x0/interrupts.c
+++ u-boot/cpu/arm920t/s3c24x0/interrupts.c
@@ -32,7 +32,7 @@
 #include <common.h>
 #if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || \
     defined(CONFIG_S3C2440) || defined (CONFIG_S3C2442) || \
-    defined (CONFIG_TRAB)
+    defined(CONFIG_S3C2443) || defined (CONFIG_TRAB)
 
 #include <arm920t.h>
 #if defined(CONFIG_S3C2400)
@@ -41,6 +41,8 @@
 #include <s3c2410.h>
 #elif defined(CONFIG_S3C2440) || defined(CONFIG_S3C2442)
 #include <s3c2440.h>
+#elif defined(CONFIG_S3C2443)
+#include <s3c2443.h>
 #endif
 
 int timer_load_val = 0;
@@ -187,6 +189,7 @@ ulong get_tbclk (void)
 #elif defined(CONFIG_SBC2410X) || \
       defined(CONFIG_SMDK2410) || \
       defined(CONFIG_SMDK2440) || \
+      defined(CONFIG_SMDK2443) || \
       defined(CONFIG_VCMA9)
 	tbclk = CFG_HZ;
 #else
Index: u-boot/drivers/usb/usbdcore_s3c2410.c
===================================================================
--- u-boot.orig/drivers/usb/usbdcore_s3c2410.c
+++ u-boot/drivers/usb/usbdcore_s3c2410.c
@@ -25,7 +25,7 @@
 #include <config.h>
 
 #if (defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) || \
-     defined(CONFIG_S3C2442)) && defined(CONFIG_USB_DEVICE)
+     defined(CONFIG_S3C2442) || defined(CONFIG_S3C2443)) && defined(CONFIG_USB_DEVICE)
 
 #include <common.h>
 
Index: u-boot/include/s3c2443.h
===================================================================
--- /dev/null
+++ u-boot/include/s3c2443.h
@@ -0,0 +1,130 @@
+/*
+ * (C) Copyright 2007 OpenMoko, Inc.
+ * Author: Harald Welte <laforge@openmoko.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __S3C2443_H
+#define __S3C2443_H
+
+/* S3C2443 device base addresses */
+#define S3C24X0_MEMCTL_BASE		0x48000000
+#define S3C24X0_USB_HOST_BASE		0x49000000
+#define S3C24X0_INTERRUPT_BASE		0x4A000000
+#define S3C24X0_DMA_BASE		0x4B000000
+#define S3C24X0_CLOCK_POWER_BASE	0x4C000000
+#define S3C24X0_LCD_BASE		0x4D000000
+#define S3C2440_NAND_BASE		0x4E000000
+#define S3C24X0_UART_BASE		0x50000000
+#define S3C24X0_TIMER_BASE		0x51000000
+#define S3C24X0_USB_DEVICE_BASE		0x49800000
+//#define USB_DEVICE_PHYS_ADR		0x49800000
+#define S3C24X3_HSMMC_BASE		0x4A800000
+#define S3C24X3_HSSPI_BASE		0x52000000
+#define S3C24X0_WATCHDOG_BASE		0x53000000
+#define S3C24X0_I2C_BASE		0x54000000
+#define S3C24X0_I2S_BASE		0x55000000
+#define S3C24X0_GPIO_BASE		0x56000000
+#define S3C24X0_RTC_BASE		0x57000000
+#define S3C2440_ADC_BASE		0x58000000
+#define S3C24X0_SPI_BASE		0x59000000
+#define S3C2440_SDI_BASE		0x5A000000
+#define S3C2443_AC97_BASE		0x5A000000
+
+#include <s3c24x0.h>
+
+/* CLOCK & POWER MANAGEMENT (see S3C2443 manual chapter 2) */
+typedef struct {
+	S3C24X0_REG32	LOCKCON0;
+	S3C24X0_REG32	LOCKCON1;
+	S3C24X0_REG32	OSCSET;
+	S3C24X0_REG32	res1;
+	S3C24X0_REG32	MPLLCON;
+	S3C24X0_REG32	res2;
+	S3C24X0_REG32	EPLLCON;
+	S3C24X0_REG32	res3;
+	S3C24X0_REG32	CLKSRC;
+	S3C24X0_REG32	CLKDIV0;
+	S3C24X0_REG32	CLKDIV1;
+	S3C24X0_REG32	res4;
+	S3C24X0_REG32	HCLKCON;
+	S3C24X0_REG32	PCLKCON;
+	S3C24X0_REG32	SCLKCON;
+	S3C24X0_REG32	res5;
+	S3C24X0_REG32	PWRMODE;
+	S3C24X0_REG32	SWRST;
+	S3C24X0_REG32	res6[2];
+	S3C24X0_REG32	BUSPRI0;
+	S3C24X0_REG32	res7[3];
+} /*__attribute__((__packed__))*/ S3C2443_CLOCK_POWER;
+
+/* NAND FLASH (see S3C2443 manual chapter 7) */
+typedef struct {
+	S3C24X0_REG32	NFCONF;
+	S3C24X0_REG32	NFCONT;
+	S3C24X0_REG32	NFCMD;
+	S3C24X0_REG32	NFADDR;
+	S3C24X0_REG32	NFDATA;
+	S3C24X0_REG32	NFMECCD0;
+	S3C24X0_REG32	NFMECCD1;
+	S3C24X0_REG32	NFSECCD;
+	S3C24X0_REG32	NFSBLK;
+	S3C24X0_REG32	NFEBLK;
+	S3C24X0_REG32	NFSTAT;
+	S3C24X0_REG32	NFECCERR0;
+	S3C24X0_REG32	NFECCERR1;
+	S3C24X0_REG32	NFMECC0;
+	S3C24X0_REG32	NFMECC1;
+	S3C24X0_REG32	NFSECC;
+	S3C24X0_REG32	NFMLCBITPT;
+} /*__attribute__((__packed__))*/ S3C2443_NAND;
+
+/* STATIC MEMORY (see S3C2443 manual chapter 5) */
+struct s3c2443_sm_bank {
+	S3C24X0_REG32	SMBIDCYR;
+	S3C24X0_REG32	SMBWSTRDR;
+	S3C24X0_REG32	SMBWSTWRR;
+	S3C24X0_REG32	SMBWSTOENR;
+	S3C24X0_REG32	SMBWSTWENR;
+	S3C24X0_REG32	SMBCR;
+	S3C24X0_REG32	SMBSR;
+	S3C24X0_REG32	SMBWSTBRDR;
+};
+
+typedef struct {
+	struct s3c2443_sm_bank bank[5];	/* 0x4f000000..0x4f0000bf */
+	S3C24X0_REG32	res[0x40];	/* 0x4f0000c0..0x4f0000ff */
+	S3C24X0_REG32	SMBONETYPER;
+	S3C24X0_REG32	SMCSR;
+	S3C24X0_REG32	SMCCR;
+} /*__attribute__((__packed__))*/ S3C2443_SMEM;
+
+
+/* MOBILE DRAM (see S3C2443 manual chapter 6) */
+typedef struct {
+	S3C24X0_REG32	BANKCFG;
+	S3C24X0_REG32	BANKCON1;
+	S3C24X0_REG32	BANKCON2;
+	S3C24X0_REG32	BANKCON3;
+	S3C24X0_REG32	REFRESH;
+	S3C24X0_REG32	TIMEOUT;
+} /*__attribute__((__packed__))*/ S3C2443_MDRAM
+
+#endif /* __S3C2443_H */
